1. Field of the Invention
The present invention relates to methods and apparatus for acquiring data representing intermittent failure of a circuit, particularly an integrated circuit.
2. The Prior Art
Debugging of very large scale integrated circuits (VLSI) is an important element of design. Probing internal nodes of integrated circuits plays an increasingly indispensable role in this process.
As device geometries shrink to and below the 1 .mu.m mark and as packing density and chip complexity increase, the problems of VLSI circuit debug become more and more difficult. Simulation and design verification software relieve many of the problems. Nevertheless, many designs do not yield fully operational, full specification parts without first undergoing lengthy, and expensive, debug phases.
Debugging a chip with any significant level of integration (LSI, VLSI, ULSI) has always been a difficult task. The recent development of electron-beam probe tools and techniques has greatly assisted in overcoming the problems involved in probing internal nodes of integrated circuits for debug and other purposes.
E-beam probing uses the principle of voltage contrast in a scanning electron microscope (SEM). A conventional SEM image is produced by raster-scanning a finely-focused beam of primary electrons over a circuit specimen as signals are applied to the specimen. Secondary electrons are thus produced and detected, resulting in a signal used to form an image of the specimen in which intensity variations represent the surface electrical potential on conductors within the specimen. For example, positive voltages appear as dark areas in the image, corresponding to fewer secondary electrons, while zero or negative voltages appear as light areas and correspond to higher secondary electron counts. See, for example, E. Menzel & E. Kubalek, Fundamentals of Electron Beam Testing of Integrated Circuits, 5 SCANNING 103-122 (1983), and E. Piles & J. Otto, Voltage Measurement Inside Integrated Circuit Using Mechanical and Electron Probes, IV SCANNING ELECTRON MICROSCOPY 1491-1500 (1985).
Commercial introduction by Schlumberger in 1987 of the "IDS 5000.TM." workstation-based, electron-beam test probe system greatly simplified E-beam probing of circuit chips and increased the efficiency of circuit debug. See S. Concina, G. Liu, L. Lattanzi, S. Reyfman & N. Richardson, Software Integration in a Workstation Based E-Beam Tester, INTERNATIONAL TEST CONFERENCE PROCEEDINGS (1986); N. Richardson, E-Beam Probing for VLSI Circuit Debug, VLSI SYSTEMS DESIGN (1987); S. Concina & N. Richardson IDS 5000: an Integrated Diagnosis System forVLSI, 7 MICROELECTRONIC ENGINEERING (1987). See also U.S. Pat. Nos. 4,706,019 and 4,721,909 to N. Richardson, which are incorporated herein by reference.
A block diagram of a prior art electron-beam test probe system is shown at 10 in FIG. 1. The system has three functional elements: an electron beam test probe 12, a circuit exerciser 14, and a data processing system 16 which includes a display terminal 18. The circuit exerciser 14 may be a conventional integrated circuit tester, such as a model "S 15.TM." tester available from Schlumberger Technologies of San Jose, Calif., which can repeatedly apply a pattern of test vectors to the specimen circuit over a bus 24 and provide an indication of whether the specimen circuit has performed in an expected manner in response to each application of the pattern. The specimen circuit is placed in the electron-beam test probe 12 so that potential measurements can be made as the test vector pattern is applied. The points at which such measurements are to be made are sent to the electron-beam test probe 12 by the data processing system 16 over a bus 22. The data processing system 16 may also be used to specify the test signal pattern used and the timing of the potential measurements relative to the test signal pattern. The electron beam test probe system is controlled by an operator who inputs commands through the display terminal 18.
SEMs used for E-beam probing, such as that in the IDS 5000 system, are equipped with high-speed beam pulsing hardware sometimes referred to as a "beam-blanker." An example of such hardware is described in U.S. Pat. No. 4,721,909. Directing a pulse electron beam at a particular node of interest provides a mode of operation much like that of a sampling oscilloscope, in which images can be produced of waveforms at one or more nodes in the specimen circuit as test vector patterns are applied to the specimen circuit. The images may be qualitative (e.g. logic state maps for digital circuit debug), or, with the aid of a secondary electron energy analyzer within the E-beam probe system, quantitative (e.g. analog signal waveforms). Acquisition of high-speed quantitative voltage waveforms with an equivalent bandwidth exceeding 1 GHz are possible. Dynamic faults in the specimen circuit may be readily observed from such waveform images.
For each point of the waveform image, a measurement is made by pulsing the electron beam at a specific time during application of the test vector pattern to the specimen circuit. Since the time needed to make a potential measurement is generally longer than the time over which the test signal pattern remains constant, stroboscopic techniques are used. That is, the electron beam is turned on for a brief period of time at a point in the test signal pattern. Each time the electron beam is so pulsed, a measurement of the potential on a node of the specimen circuit is made. Since a single measurement has insufficient statistical accuracy to allow an accurate determination of the potential, measurements made over many repetitions of the test vector pattern are averaged. Coordination of the electron-beam pulses with the test vector pattern may be effected by a trigger generator circuit of the electron-beam test probe system under control of data processing system 16.
FIG. 2 shows a functional block diagram of portions of an electron beam test probe system configured in prior art manner for acquisition of waveform images from a circuit under test. A trigger signal from tester 14 is provided to a timing controller 30, which in turn supplies beam-pulse timing signals to the electro-optics of the electron-beam probe 12. Potential measurement signals from the electron-beam probe 12 are digitized by an analog-to-digital converter (ADC) 32 under control of a timing signal synchronized with the beam pulse timing signals, and supplied to one input of an arithmetic logic unit (ALU) 34.
A second input of ALU 34 receives digital data from a data buffer 36. ALU 34 is a conventional device which adds the digital data provided at its respective inputs and provides the sum at its output. The sum at the output of ALU 34 is returned to data buffer 36 under control of a data buffer address controller 38. Data bus address controller 38 communicates with timing controller 30 and with a microprocessor 40 via a communication interface 42. Data buffer address controller 38 keeps track of which data relates to which point in the waveform when such data is stored in data buffer 36 so that the data may be composed as a waveform image for display.
In one prior art method of waveform acquisition, the desired waveform image may be made up of values at a number n (for example, 500) of points during the test vector pattern. Each point is assigned an address in data buffer 36. As shown in the timing diagram of FIG. 3, a trigger signal pulse 40 from tester 14 causes timing control circuit 30 to supply a beam pulse 42 to test probe 12 at a time t.sub.1 following trigger pulse 40. When a succeeding trigger pulse 44 is produced by tester 14, timing control circuit 30 produces a further beam pulse 46 at a time t.sub.1 after trigger pulse 44. Each trigger pulse (40, 44, etc.) typically represents one repetition of the test vector pattern applied to the specimen circuit. Measurements are repeatedly taken at a time t.sub.1 following the trigger pulses until a sufficient number of pulses have been acquired and averaged at that time in the test vector sequence to give a meaningful measurement. This may require 10,000 or more repetitions of the test vector sequence for each point in the waveform to be acquired. The process is repeated for a second point in the waveform represented by a time t.sub.2 following each of a number of trigger pulses. The repetition continues until an nth point in the waveform is acquired, representing a time t.sub.n following each of a number of trigger pulses.
It can be seen that for even a relatively simple circuit under test, tens of thousands or even hundreds of thousands of repetitions of the test vector pattern may be needed to acquire the data represented in a waveform image.
A rule of thumb commonly applied for setting acquisition parameters is that the duty cycle (the trigger period divided by the beam pulse width) should be less than about 10,000 to 100,000. For example, a 10 MHz microprocessor specimen circuit has a 100 nanosecond clock period; applying a 10,000-vector test pattern means that one complete repetition of the test pattern would require 1 millisecond. To obtain a meaningful measurement at a 10 MHz specimen clock speed, one might employ a 10 nanosecond beam pulse, resulting in a duty cycle of about 100,000. As duty cycles increase, leakage currents and other measurement limitations result in degraded measurement accuracy.
Data acquisition time is also a very real concern, particularly with the lengthy test vector patterns require to exercise ever more complex integrated circuits. With the prior art method of acquiring waveform data illustrated in the timing diagram of FIG. 3, the number of repetitions of the test pattern required to obtain a waveform is equal to the number of points n in the desired waveform multiplied by the number of samples to be averaged at each point in the waveform. For example, if 500 samples are to be averaged at each point in a waveform comprising 500 points, 25,000 repetitions of the test vector sequence are required to acquire the waveform. With the 10 MHz microprocessor specimen mentioned above, and using a 1 millisecond electron-beam pulse, acquiring a waveform of 500 points with 500 beam pulses for each point in the waveform, 250 seconds (more than 4 minutes) would be required for one pass at acquiring the waveform. Depending upon the circuit and the desired measurement, multiple passes might be required to obtain a suitable waveform. FIG. 4 shows a timing diagram of a further prior art waveform acquisition technique, sometimes called "interlacing" or "burst mode imaging." The waveform acquisition technique of FIG. 4 can greatly reduce the number of repetitions of the test vector pattern and, hence, the time needed to acquire a given waveform over the described with reference to FIG. 3. At a time t.sub.1 following a trigger pulse 50, a beam pulse 52 is produced. Further beam pulses 54, 56, etc., are produced at an interval 4.delta.t following pulse 52, where .delta.t represents the time interval between points in the desired waveform. Thus, data is acquired for one fourth of the points in the desired waveform with each repetition of the test pattern. When a desired number of measurements at those points in the waveform have been averaged, the beam pulses are then retarded by a time .delta.t such that the first beam pulse 60 follows a a trigger pulse by a time t.sub.2, where t.sub.2 equals t.sub.1 +.delta.t. Data is therefore acquired for an additional one quarter of the points on the desired waveform for each repetition of the test pattern. After many repetitions of the test pattern, the beam pulses are again retarded by a time .delta.t for acquisition of data at a third quarter of the points in the desired waveform. After many repetitions of the test pattern, the beam pulses are again retarded by a time .delta.t for acquistion of data for the remaining points in the desired waveform. In the illustrative example given, only four repetitions of the test pattern are required to obtain a single measurement for each point on the desired waveform. Thus, if a waveform of 500 points is desired, with 500 measurements averaged at each point, a total of 4.times.500=2,000 repetitions of the test pattern are required to acquire the waveform, using suitable high-speed hardware to process and store the acquired data.
FIG. 5 shows a further prior art configuration of an electron-beam test probe system for acquisition of waveform images in either a synchronous or an asynchronous mode of operation. In the synchronous mode (used for logic analysis when timing information is less critical), the signal on the selected internal node or conductor of the specimen circuit is sampled once per fixed interval of time, typically the period of a user-supplied (external) sync clock signal. The samples so acquired indicate the logic state of the node during each clock period. Synchronous sampling can be performed with external clock rates of, for example, 10 KHz to 200 MHz. However, the maximum beam pulse repetition rate (which is the real sampling rate) is limited by the scintillator bandwidth of the electron-beam test probe which may be, for example, 10 MHz. An interlaced sampling scheme may be used to increase the effective sampling rate. For example, if the external clock frewquency is 100 MHz, during the first pass through the test pattern the electron beam may be pulsed on clock edges 0, 10, 20, 30, etc. During the next pass through the test pattern the beam may be pulsed on clock edges 1, 11, 21, 31, etc. Repeating this 10 times will result in the complete waveform.
The interlacing may be accomplished by a counter/gate & multiplexer circuit shown in block form in FIG. 5, which may be incremented by the external sync clock signal. At the start of each test pattern sequence, the counter is re-set by the trigger signal from the circuit exerciser, via a trigger delay circuit 72. The gate of circuit 70 compares the current clock edge number to the set of clock signal edges for which the electron beam is to be pulsed. If a match occurs, the clock edge is allowed to pass; otherwise it is gated off. The acquisition clock edges output by circuit 70 are passed to a pulse generator 74 which supplies pulses to turn on the electron beam. The output of circuit 70 may also be used to generate addresses for the data buffer memory so that the sample corresponding to clock "1" is stored in location "1" of the buffer memory, and so on.
In the asynchronous (or timing analysis) mode, the signal on the node being probed may be sampled more frequently than the clock frequency of the signal on the node to acquire more accurate timing information, e.g., to detect unexpected signal variations as well as logic level transitions in the signal being observed. For example, a signal with a period of 100 ns can be sampled at 2 ns intervals. This mode can be implemented by means of a restartable oscillator 76 which, when stopped and restarted by a trigger signal, will always start to oscillate exactly in phase with the trigger signal. Once the asynchronous clock signal is generated by oscillator 76, it may be divided in a frequency divider 78 to produce an asynchronous clock signal used for interlacing in the same manner as the sync clock signal is used in the synchronous mode. The asynchronous clock frequency may be set, for example, from 1 MHz to 200 MHz.
The buffer memory bandwidth must be high enough to accept a read-modify-write access at a rate of, for example, every 100 ns. This may be implemented with low cost SRAMs configured in a low-order interleaved memory system as shown in the prior art configuration of FIG. 6. The memory may be divided into eight independent columns 80-96, each of which has its own arithmetic logic unit (ALU) and memory controller. An address generator 98 controls storage locations within the memory columns via address latches 100-116. With such a configuration, each incoming sample may be routed to one of the eight columns depending on the least three bits of the corresponding clock edge number (which may also be used as the memory address). It has been found that, with one such arrangement, the read-modify-write cycle takes 400 ns while the incoming samples can arrive at a maximum rate of one per 100 ns. So, at any time, up to four of these columns will be simultaneously but independently performing a read-modify-write access. The memory is preferably capable of storing 256K 16-bit samples in a buffer accessible to the data processing system of the electron-beam test probe system.
A display is preferably provided on the display terminal of the electron-beam test probe system in a form modeled on a conventional logic analyzer. Such a display provides the user with a tool whose operation is, as far as possible, intuitive by analogy with the logic analyzer model. It is preferred that extensive use of pop-up menus and icons be made and, wherever possible, the user be shielded from the physics of the actual measurement process.
The prior art methods and arrangements described above provide a single channel of waveform acquisition. Prior art multi-channel tools are also known in which multiple "probes" (probe icons) may be placed on the SEM tool window of the display terminal of the electron-beam test probe system. See, for example S. Concina and N. Richardson, Workstation Driven E-Beam Prober, INTERNATIONAL TEST CONFERENCE PROCEEDINGS, pp. 554-560 (1987). That is, in the window displaying a live voltage-contrast image of the specimen circuit, an icon is placed where the specimen circuit is to be probed. The system then sequentially acquires a logic waveform at for each probe location and displays the waveform images.
FIG. 7 is a photograph of an electron-beam test probe system display showing a voltage contrast image of conductors of a specimen circuit along with waveform images representing acquired signals at user-specified nodes of the specimen circuit. In the background window is a voltage contrast image of conductors of the specimen circuit. Probe icons (such as those labeled 0, 3, 4, 5, 6 and 7 in FIG. 7) placed in the image by the user show the conductors to be measured. The electron-beam test probe system can then direct the electron beam to the correct nodes to determine the logic state of the conductor. The sampling rate of the beam is kept close to the maximum allowable, for example, 10 MHz. This is achieved by generating multiple beam pulses per trigger signal and using high-speed digital signal processing to capture, process and manipulate the resulting data stream in conventional fashion as described above. The logic waveform for a single conductor can typically be measured in much less than one second (but is of course still dependent on the trigger rate, which is related to the test vector pattern length). Thus, the state of a complete 16 or 32-bit bus can be readily determined in a few seconds. Once data has been acquired, it can be compared directly with either similar results from another device or simulation and test vectors.
Shown in the foreground window of FIG. 7 is a series of waveform images wave0-wave7 acquired at corresponding selected locations 0-7 of the specimen circuit (icons representing probe locations 1 and 2, corresponding to waveform images wave1 and wave2, are not seen in FIG. 7 as they are hidden by the "Logic Analyzer" window in the foreground). Light-colored blocks at the right-hand portion of waveform image wave2 represent acquired data which is inconclusive as to whether the probed location is at a logic "1" or logic "0" state.
Electron-beam test probe systems may be employed not only to acquire qualitative (logic state) waveforms as described above, but also to acquire quantitative (voltage level, or analog) waveforms. FIG. 8 shows in schematic block form a prior-art example of how this may be done. The filter electrode 120 of the electron-beam column is placed between the specimen device under test (DUT) 122 and the scintillator 124 of the electron-beam column. A voltage V is applied to electrode 120 such that the secondary electrons 126 experience a retarding field. The number of electrons with sufficient energy to overcome the potential barrier presented by electrode 120 is governed by the surface potential of the specimen 122. A feedback loop formed by a gate 132 and an integrator 134, and supplied by a constant-current source 130, is used to vary the potential of the filter electrode in a manner that maintains constant the number of electrons detected and, therefore the current of photomultiplier tube (PMT) 128. Gate 132 is closed once during each beam-pulse interval, so that the voltage on the filter electrode 120 tracks variations in the surface potential of the specimen 122.
An underlying premise of the waveform acquisition techniques described above is that the specimen circuit always fails in exactly the same way, i.e., that the failure is repeated during each repetition of the test pattern, or at least during a high enough percentage of the repetitions of the test pattern that averaging of the acquired data produces a waveform image from which the failure can be diagnosed. In practice, it has been found that perhaps 75%-80% of IC failures are of this type.
However, some ICs fail only intermittently, e.g., one or two times out of 10 repetitions of the test pattern. In such case, it is important to know whether acquired data represents the expected ("correct" or "good") performance of the specimen circuit or represents a "failing" performance of the specimen circuit, since averaging data from both good and failing performances often does not provide a waveform image useful in diagnosing the causes of the failing performances. Traditionally, it has not been possible to address this class of problem with electron-beam test probe systems because it is, by definition, not possible to cause the device to fail repeatedly. Instead, engineers were forced to change device operating parameters (such as supply voltage, operating speed or temperature) in such a way that the failure mechanism was not intermittent. This is time-consuming, often inconvenient and sometimes impossible.
It is an object of an embodiment of the present invention to provide methods and apparatus for acquiring data representing intermittent failure of a specimen circuit, while rejecting data from good performances of the specimen circuit, such that waveform images representing failing performances may be produced. Such images can be an invaluable aid in diagnosing the sources and/or causes the intermittent failure.